1. Field of the Invention
The present invention relates to circuitry for preliminary processing of the raw output signal from a CCD image sensor. More particularly, the invention is (or includes) a correlated double sampler circuit including a single amplifier, having ping-pong architecture, and capable of processing a raw output signal from a CCD image sensor to generate an analog signal indicative of the value of each pixel of a sensed image.
2. Description of the Related Art
CCD (charge coupled device) image sensors are widely used to convert images into electronic signals that can be captured, transmitted, stored and displayed. Camcorders and digital still cameras typically use CCDs.
A CCD divides an image into a large number of discrete cells or pixels. The raw output signal produced by a CCD image sensor has a waveform of the type shown in FIG. 3. The FIG. 3 signal is a series of discrete analog voltage levels. The high voltage level (which immediately precedes the low level portion of each cycle) is commonly called the xe2x80x9creset levelxe2x80x9d, while the lower voltage level is commonly called the xe2x80x9csignal levelxe2x80x9d, as indicated in FIG. 3. The difference between a signal level and its preceding reset level indicates the amount of light (typically of a particular color) that has fallen on one particular pixel of the image sensor.
One characteristic of CCDs is that each reset level is slightly different from the others due to noise. For this reason, it is important to quantify the difference between the signal level and its preceding reset level; not the absolute value of the signal level. It is common practice in systems that use CCDs to employ a circuit called a correlated double sampler (CDS) to sample and hold the difference between these two voltage levels (for each pixel of the sensed image).
FIG. 1 is a simplified block diagram of a conventional circuit, which includes two CDS circuits (CDS1 and CDS2) and has xe2x80x9cping-pongxe2x80x9d architecture,xe2x80x9d for preliminary processing of the raw output signal (labeled xe2x80x9cINxe2x80x9d) of a CCD image sensor. The expression xe2x80x9cping-pong architecturexe2x80x9d denotes that the FIG. 1 circuit is configured and controlled to process consecutive samples (of the signal IN) at the rate of one sample per clock cycle, with CDS2 processing every even sample and CDS1 processing every odd sample. This architecture provides an efficient solution to the problem of how to accomplish three sequential functions (clamp, sample, and hold) in response to two clock edges only per clock cycle. Another advantage of this architecture is that the hold cycle during which amplifier PGA takes the difference between the reset level and signal level (of a single sampled pixel) and presents this difference as output signal OUT can be a full clock cycle long.
It is well known to implement correlated double samplers (CDS""s). For example, the AD9801 integrated circuit product manufactured by Analog Devices, implements the FIG. 1 circuit, which in turn includes two CDS""s (CDS1 and CDS2). This implementation of the FIG. 1 circuit is described in C. Mangelsdorf, et al., xe2x80x9cA CMOS Front-End for CCD Cameras,xe2x80x9d Paper FA 11.5, Proceedings of the 1996 IEEE International Solid-State Circuits Conference (pp. 146-147 and 186-187).
In FIG. 1, CDS1 includes circuitry implementing identical sample and hold circuits 1 and 2 and subtraction unit 5, the circuits 1 and 2 being connected in parallel between the input node and subtraction unit 5. CDS2 includes circuitry implementing identical sample and hold circuits 3 and 4 (which are identical to circuits 1 and 2) and subtraction unit 6, the circuits 3 and 4 being connected in parallel between the input node and subtraction unit 6. Each of circuits CDS1 and CDS2 is a sample and hold amplifier (which consumes power and has an offset value). Switch S1 selectively passes the output of CDS1 or CDS2 to amplifier 7, and the output of amplifier 7 is asserted to sample and hold circuit 8. The amplified signal output from amplifier 7 (the xe2x80x9cOUTPUTxe2x80x9d signal) is typically asserted by circuit 8 to an analog-to-digital converter (not shown).
Elements 9, 10, and 13 (connected as shown) comprise a black level correction loop for CDS1, and elements 11, 12, and 14 (connected as shown) comprise a black level correction loop for CDS2. Each black level correction loop provides feedback to set the output voltage OUTPUT to a known value for CCD pixel outputs of zero value (black).
The difference between portions of the OUTPUT signal indicative of black pixels (i.e., corresponding to masked portions of the CCD sensor) which have been processed by CDS1, and a desired output signal, are integrated in integration circuit 9. The output of circuit 9 is amplified in inverse amplifier 10 (whose gain is the inverse of amplifier 7""s gain) and fed back to one input of addition unit 13, and unit 13 adds the output of amplifier 10 to the output of unit 5 being asserted to the other input of unit 13. The difference between portions of the OUTPUT signal indicative of black pixels which have been processed by CDS2, and a desired output signal, are integrated in integration circuit 11 (which is identical to circuit 9). The output of circuit 11 is amplified in inverse amplifier 12 (whose gain is the inverse of amplifier 7""s gain) and fed back to one input of addition unit 14, and unit 14 adds the output of amplifier 10 to the output of unit 6 being asserted to the other input of unit 14.
In each of correlated double samplers CDS1 and CDS2, three functions must be executed during each clock cycle: sampling of the reset level, sampling of the signal level, and taking the difference between the two samples. The ping/pong approach, in which every odd sample of input signal IN (i.e., the first sample, the third sample, and so on) is processed by a first (ping) amplifier CDS1 and every even sample is processed by a second (pong) amplifier CDS2, is an efficient solution to the problem of how to accomplish the three sequential functions in response to only two clock edges per amplifier per clock cycle.
Waveforms of the periodic control signals needed to operate the circuit of FIG. 1 are shown in FIG. 1A. On the falling edge of control signal Q1, CDS1 samples the input signal IN and asserts this sample (which is the sampled reset level) to subtraction unit 5. On the falling edge of control signal Q2, CDS1 again samples the input signal IN and asserts this sample (which is the sampled signal level) to subtraction unit 5, and a control signal (not shown) is asserted to switch S1 to cause switch S1 to couple the output of CDS1 to amplifier 7. Then, while switch remains in this state, CDS2 samples the input signal IN on the falling edge of control signal Q3 and asserts this sample (which is the sampled reset level for the next pixel) to subtraction unit 6. Then, on the falling edge of control signal Q4, CDS2 again samples the input signal IN and asserts this sample (which is the sampled signal level for the same pixel) to subtraction unit 6, and another control signal (not shown) is asserted to switch S1 to cause switch S1 to couple the output of CDS2 to amplifier 7 (thereby decoupling the output of CDS1 from amplifier 7). An advantage of the FIG. 1 implementation is that the hold cycle during which each of amplifiers CDS1 and CDS2 takes the different between a reset level and a signal level and presents this difference as an output signal (through switch S1 to amplifier 7) is a full clock cycle in duration (such a full clock consists of a half cycle in which Q1 is high and a half cycle in which Q2 is high, or a half cycle in which Q3 is high and a half cycle in which Q4 is high).
A problem with the FIG. 1 circuit is that each of sample and hold amplifiers CDS1 and CDS2 has its own offset voltage. Since each of CDS1 and CDS2 has a different offset voltage, two separate black level correction loops must be employed, one for each of circuits CDS1 and CDS2.
Another problem with conventional implementations of the FIG. 1 circuit is that the outputs of each of circuits CDS1 and CDS2 is referenced to ground (single ended). As a result, the FIG. 1 circuit has a poor power supply rejection ratio (PSRR).
U.S. Pat. Nos. 5,757,440 and 5,736,886 disclose implementations of the FIG. 1 circuit and variations thereon. For example, FIG. 8 of U.S. Pat. No. 5,757,440 discloses a variation on the FIG. 1 circuit which has ping-pong architecture and includes four sample and hold circuits (96, 98, 100, and 102) and a single subtraction element (xe2x80x9cdifference elementxe2x80x9d 127). However, there is no suggestion in either reference that a circuit having ping-pong architecture (for preliminary processing of a CCD image sensor""s raw output) should be implemented to include only a single amplifier (having a single offset), and no suggestion as to how to implement such a single amplifier circuit.
It is known to implement a pipelined circuit to include a single operational amplifier (xe2x80x9cop ampxe2x80x9d) which is shared between adjacent stages of the pipelined circuit, and to implement other circuits including such a shared op amp. See, for example, Yu and Lee, xe2x80x9cA 2.5-V, 12-b, 5-MSample/s Pipelined CMSO ADC,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 31, No. 12 (December 1996), pp. 1854-1861.
However, until the present invention, such an amplifier sharing technique has not been applied to a circuit implementing a CDS function for CCD processing applications (e.g., to overcome the limitations and disadvantages of conventional CDS circuits such as that described above with reference to FIG. 1).
In a class of preferred embodiments, the invention is a correlated double sampler (CDS) circuit having a ping/pong architecture, which includes only a single active amplifier (and thus a single offset voltage associated with the amplifier). In another class of embodiments, the invention is a CCD image sensor output processing circuit including such a CDS circuit. The CDS circuit includes capacitor and switch circuitry (comprising switches and capacitors, but not an amplifier) coupled between the input node (at which the raw CCD sensor output is received), the input of the amplifier, and the output of the amplifier.
In one cycle of operation during processing of the raw output of a CCD image sensor, the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set of control signals is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set of control signals is indicative of the value of the next pixel of the image. In preferred implementations, each set of control signals consists of a clamp signal, a sample signal, and a hold signal. Since the output signal of the CDS circuit has the same offset voltage for all pixels of an image (including both even and odd pixels), black level correction can be implemented using only one black level correction feedback loop. Use of a single amplifier (rather than two or more amplifiers as in the prior art) and one black level correction loop (rather than two black level correction loops) reduces power consumption.
In preferred implementations, the amplifier of the inventive CDS circuit is an op amp which produces a differential output and therefore has a better power supply rejection ratio than does the prior art.
Preferably, the invention is implemented with CMOS technology as an integrated circuit (or portion of an integrated circuit).
The inventive circuit preferably has a continuous differential output. In operating the circuit, it is not important to cancel amplifier offset since the entire signal chain is in an offset adjusting feedback loop. It is important to keep the offset the same for every input signal sample (including samples of even pixels and samples of odd pixels) to avoid xe2x80x9ceven samplexe2x80x9d-to-xe2x80x9codd samplexe2x80x9d offset differences, and to minimize power consumption.